Semiconductor memory devices having closely spaced bit lines

ABSTRACT

The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation application of and claimspriority from U.S. patent application Ser. No. 14/989,955, filed on Jan.7, 2016, which claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2015-0111749, filed on Aug. 7, 2015 in the KoreanIntellectual Property Office, the entire contents of which are herebyincorporated herein by reference in their entireties.

BACKGROUND

The inventive concepts relate to semiconductor memory devices.

Semiconductor devices have been highly integrated to provide increasedperformance and reduced manufacturing costs. Integration densities ofsemiconductor devices may directly affect the costs of the semiconductordevices. An integration density of a two-dimensional (2D) or planarsemiconductor memory device may be mainly determined by an area of aunit memory cell. Thus, the integration density of the 2D semiconductormemory device may be greatly affected by a technique of forming finepatterns. However, since extremely high-priced apparatuses are needed toform very fine patterns, the integration density of 2D semiconductormemory devices may continue to increase but may be still limited. Thus,semiconductor memory devices including three-dimensionally arrangedmemory cells have been developed.

SUMMARY

Embodiments of the inventive concepts may provide semiconductor memorydevices having improved electrical characteristics and integrationdensity.

In one aspect, a semiconductor memory device includes a substrate havingan upper surface that extends in a first direction and in a seconddirection that is perpendicular to the first direction; a memory cellarray on the substrate; a first page buffer; a second page buffer; and aplurality of bit lines that extend in the second direction to at leastpartly cross the memory cell array. The bit lines include a plurality offirst bit lines that are electrically connected to the first page bufferand a plurality of second bit lines that are electrically connected tothe second page buffer. The first bit lines and the second bit lines arealternately and repeatedly arranged in the first direction.

In an embodiment, the first bit lines may have respective first endportions that are adjacent a first side of the memory cell array andrespective second end portions that are adjacent a second side of thememory cell array, and the second bit lines may have respective firstend portions that are adjacent the first side of the memory cell arrayand respective second end portions that are adjacent the second side ofthe memory cell array. In such embodiments, the semiconductor memorydevice may also include a plurality of first connection contacts thatextend in a third direction that is perpendicular to the first andsecond directions that connect the first end portions of the first bitlines to the first page buffer and a plurality of second connectioncontacts that extend in a third direction that connect the first endportions of the second bit lines to the second page buffer.

In an embodiment, the semiconductor memory device may further include aplurality of first connection conductive lines that extend in the seconddirection, the first connection conductive lines electrically connectedto respective ones of the first bit lines; and a plurality of secondconnection conductive lines that extend in the second direction, thesecond connection conductive lines electrically connected to respectiveones of the second bit lines.

In an embodiment, an average width of a first of the first connectionconductive lines in the first direction may be greater than an averagewidth in the first direction of a first of the first bit lines, and anaverage width of a first of the second connection conductive lines inthe first direction may be greater than an average width in the firstdirection of a first of the second bit lines.

In an embodiment, a first distance between adjacent ones of the firstconnection conductive lines may be greater than a second distancebetween adjacent ones of the bit lines, and a third distance betweenadjacent ones of the second connection conductive lines may be greaterthan the second distance.

In an embodiment, a pitch of the first connection conductive lines maybe greater than a pitch of the bit lines, and a pitch of the secondconnection conductive lines may be greater than the pitch of the bitlines.

In an embodiment, the substrate may include a first connection region, asecond connection region and a circuit region therebetween, the memorycell array may be disposed on the circuit region, and the first bitlines may extend onto the first connection region and the second bitlines may extend onto the second connection region.

In an embodiment, a maximum width of a first portion of a first of thefirst bit lines that is on the first connection region may exceed amaximum width of a second portion of the first of the first bit linesthat crosses the memory cell array, and a maximum width of a firstportion of a first of the second bit lines that is on the secondconnection region may exceed a maximum width of a second portion of thefirst of the second bit lines that crosses the memory cell array.

In an embodiment, a maximum width of a first portion of a first of thefirst connection conductive lines that is on the first connection regionmay exceed a maximum width of a second portion of the first of the firstconnection conductive lines that is under the memory cell array, and amaximum width of a first portion of a first of the second connectionconductive lines that is on the second connection region may exceed amaximum width of a second portion of the first of the second connectionconductive lines that is under the memory cell array.

In an embodiment, a first of the first bit lines may extend a differentdistance in the second direction onto the first connection region thandoes a second of the first bit lines that is adjacent the first of thefirst bit lines.

In an embodiment, a first of the first connection conductive lines mayextend a different distance in the second direction onto the firstconnection region than does a second of the first connection conductivelines that is adjacent to the first of the first connection conductivelines, and a first of the second connection conductive lines may extenda different distance in the second direction onto the second connectionregion than does a second of the second connection conductive lines thatis adjacent to the first of the second connection conductive lines.

In an embodiment, the memory cell array may include a semiconductorlayer; a stack structure including a plurality of electrodes that arestacked on the semiconductor layer in a third direction that isperpendicular to the first direction and to the second direction; aplurality of active pillars penetrating the stack structure in the thirddirection; and a data storage element disposed between each of theactive pillars and the electrodes.

In an embodiment, the stack structure may comprise a first of aplurality of stack structures that are spaced apart from each other inthe second direction, and the semiconductor memory device may furtherinclude an upper insulating layer on outer sidewalls of the outermostones of the stack structures, the upper insulating layer extending ontothe first and second connection regions; first connection contactspenetrating a first portion of the upper insulating layer that is on thefirst connection region, the first connection contacts electricallyconnecting the first bit lines to the first connection conductive lines;and second connection contacts penetrating a second portion of the upperinsulating layer that is on the second connection region, the secondconnection contacts electrically connecting the second bit lines to thesecond connection conductive lines.

In an embodiment, lower ends of the first connection contacts maydirectly contact respective ones of a plurality of first connectionconductive pads, and lower ends of the second connection conductivecontacts may directly contact respective ones of a plurality of secondconnection conductive pads.

In an embodiment, the first and second connection conductive pads mayhave widths that are greater than widths of the first and secondconnection conductive lines.

In an embodiment, the memory cell array may comprise a semiconductorlayer; a stack structure including a plurality of electrodes that arestacked on the semiconductor layer in a third direction that isperpendicular to the first direction and to the second direction; and aplurality of active pillars penetrating the stack structure in the thirddirection, where each of the active pillars includes a pair of verticalportions that penetrate the stack structure and a horizontal portionthat connects bottom ends of the vertical portions to each other.

In an embodiment, the semiconductor memory device may further include aplurality of first lower contacts and a plurality of second lowercontacts, the first and second lower contacts extending in a thirddirection that is perpendicular to the first direction and to the seconddirection; and a plurality of first connection contacts and a pluralityof second connection contacts, the first and second connection contactsextending in the third direction. In such embodiments, the firstconnection conductive lines may directly contact respective ones of thefirst lower contacts and respective ones of the first connectioncontacts and the second connection conductive lines may directly contactrespective ones of the second lower contacts and respective ones of thesecond connection contacts.

In an embodiment, the first and second page buffers may be part of alogic circuit that is formed on the substrate, and the semiconductormemory device may further include an insulating layer on the logiccircuit opposite the substrate, where the memory cell array is on theinsulating layer opposite the logic circuit.

In an embodiment, each of the first and second bit lines may include afirst conductive material, and each of the first and second connectionconductive lines may include a second conductive material that has amelting point that is higher than a melting point of the firstconductive material. In some such embodiments, the first conductivematerial may include copper (Cu) or aluminum (Al) and the secondconductive material may include tungsten (W).

In another aspect, a semiconductor memory device includes a substratehaving a circuit region and first and second connection regions onopposed sides of the circuit region, the substrate including an uppersurface that extends in a first direction and in a second direction thatis perpendicular to the first direction; a memory cell array on thesubstrate; a plurality of bit lines that extend in the second directionto at least partially cross the circuit region, the bit lines spacedapart from each other in the first direction; and a plurality ofconnection conductive lines that extend in the second direction and thatare electrically connected to respective ones of the bit lines. Anaverage width of a first of the connection conductive lines is greaterthan an average width of the one of the bit lines to which the first ofthe connection conductive lines is electrically connected.

In an embodiment, the semiconductor memory device may further include apage buffer circuit that has a first page buffer and a second pagebuffer, and the connection conductive lines may comprise firstconnection conductive lines and second connection conductive lines.

In an embodiment, the bit lines may comprise first bit lines that areelectrically connected to the first page buffer by respective ones ofthe first connection conductive lines and second bit lines that areelectrically connected to the second page buffer by respective ones ofthe second connection conductive lines, where the first bit lines andthe second bit lines are alternately and repeatedly arranged in thefirst direction.

In an embodiment, the semiconductor memory device may further include aplurality of first lower contacts and a plurality of second lowercontacts that extend in a third direction that is perpendicular to thefirst direction and to the second direction; and a plurality of firstconnection contacts and a plurality of second connection contacts thatextend in the third direction. In such embodiments, each firstconnection conductive line may directly contact a respective one of thefirst lower contacts and a respective one of the first connectioncontacts, and each second connection conductive line may directlycontact a respective one of the second lower contacts and a respectiveone of the second connection contacts.

In an embodiment, each bit line may have a first end portion that isadjacent a first side of the memory cell array and a second end portionthat is adjacent a second side of the memory cell array, and the firstend portions of the first bit lines may directly contact respective onesof the first connection contacts and the second end portions of thesecond bit lines may directly contact respective ones of the secondconnection contacts.

In an embodiment, the first end portions of the first bit lines may bealigned along a first imaginary line that extends in the first directionand the first end portions of the second bit lines may be aligned alonga second imaginary line that extends in the first direction, and thefirst imaginary line may be spaced apart from the second imaginary linein the second direction.

In an embodiment, the first end portions of the first bit lines may havean expanded width in the first direction.

In an embodiment, the first end portions of a first subset of the firstbit lines may be aligned along a first imaginary line that extends inthe first direction, the first end portions of a second subset of thefirst bit lines may be aligned along a second imaginary line thatextends in the first direction, and the first end portions of the secondbit lines may be aligned along a third imaginary line that extends inthe first direction, the first, second and third imaginary lines beingspaced apart from each other in the second direction.

In an embodiment, the first end portions of at least some of the firstbit lines may have an expanded width in the first direction.

In an embodiment, portions of the first connection conductive lines thatdirectly contact the respective first connection contacts may have anexpanded width in the first direction.

In an embodiment, the first and second bit lines may include a firstconductive material, and the first and second connection conductivelines may include a second conductive material that has a melting pointthat is higher than a melting point of the first conductive material. Insuch embodiments, the first conductive material may include copper (Cu)or aluminum (Al) and the second conductive material may include tungsten(W).

In an embodiment, the memory cell array may comprise a stack structurethat includes plurality of gate electrodes that each extend in the firstdirection and that are stacked in the third direction on the substrate.

In an embodiment, the semiconductor memory device may further include aninsulating layer that penetrates the stack structure, where at leastsome of the first connection contacts penetrate the insulating layer.

In an embodiment, first end portions of the first bit lines may extendonto the first connection region but second end portions of the firstbit lines may not extend onto the second connection region, and secondend portions of the second bit lines may extend onto the secondconnection region but first end portions of the second bit lines may notextend onto the first connection region.

In another aspect, a semiconductor memory device includes a substratehaving an upper surface that extends in a first direction and in asecond direction that is perpendicular to the first direction; a logiccircuit on the upper surface of the substrate, the logic circuitincluding a first page buffer; and a memory cell array on the logiccircuit opposite the substrate. The memory cell array may include asemiconductor layer; a plurality of stack structures that are spacedapart from each other in the second direction, the stack structuresincluding a plurality of electrodes that are stacked on thesemiconductor layer in a third direction that is perpendicular to thefirst and second directions; a plurality of first bit lines that extendin the second direction to at least partially cross the stackstructures, the first bit lines spaced apart from each other in thefirst direction; and a plurality of insulating layers that extend in thefirst direction that are provided between adjacent ones of the stackstructures. The semiconductor memory device may further include aplurality of first connection contacts that penetrate a first of theinsulating layers, the first connection contacts electrically connectingrespective ones of the first bit lines to the first page buffer

In an embodiment, the memory cell array may further include a pluralityof second bit lines that extend in the second direction to at leastpartially cross the stack structures, the first and second bit linesalternately and repeatedly arranged in the first direction. In suchembodiments, the semiconductor memory device may further include asecond page buffer; and a plurality of second connection contacts thatelectrically connect respective ones of the second bit lines to thesecond page buffer.

In an embodiment, the semiconductor memory device may also include aplurality of first connection conductive lines that extend in the seconddirection, the first connection conductive lines electrically connectingto respective ones of the first bit lines to the first page buffer; anda plurality of second connection conductive lines that extend in thesecond direction, the second connection conductive lines electricallyconnecting respective ones of the second bit lines to the second pagebuffer.

In an embodiment, an average width of a first of the first connectionconductive lines in the first direction may be greater than an averagewidth in the first direction of a first of the first bit lines, and anaverage width of a first of the second connection conductive lines inthe first direction may be greater than an average width in the firstdirection of a first of the second bit lines.

In an embodiment, a first distance between adjacent ones of the firstconnection conductive lines may be greater than a second distancebetween adjacent ones of the first and second bit lines, and a thirddistance between adjacent ones of the second connection conductive linesmay be greater than the second distance.

In an embodiment, a pitch of the first connection conductive lines maybe greater than a pitch of the combination of the first and second bitlines, and a pitch of the second connection conductive lines may begreater than the pitch of the combination of the first and second bitlines.

In an embodiment, the second connection contacts may penetrate a secondof the insulating layers.

In one aspect, a semiconductor device may include a substrate includinga circuit region and first and second connection regions respectivelydisposed at both sides of the circuit region opposite to each other, alogic structure including a logic circuit disposed on the circuit regionand a lower insulating layer covering the logic circuit, and a memorystructure on the logic structure. The logic circuit may include a firstpage buffer disposed adjacently to the first connection region and asecond page buffer disposed adjacently to the second connection region.The memory structure may include bit lines extending onto at least oneof the first and second connection regions. The bit limes may includefirst bit lines electrically connected to the first page buffer, andsecond bit lines electrically connected to the second page buffer. Thefirst bit lines and the second bit lines may be alternately andrepeatedly arranged in a direction intersecting a longitudinal directionof the first and second bit lines.

In an embodiment, the logic structure may further include firstconnection conductive lines electrically connecting the first pagebuffer to the first bit lines and extending onto the first connectionregion, and second connection conductive lines electrically connectingthe second page buffer to the second bit lines and extending onto thesecond connection region. The first connection conductive lines mayoverlap with the first bit lines when viewed from a plan view, and thesecond connection conductive lines may overlap with the second bit lineswhen viewed from a plan view.

In an embodiment, a distance between the first connection conductivelines and a distance between the second connection conductive lines maybe greater than a distance between the first and second bit linesadjacent to each other.

In an embodiment, a width of each of the first connection conductivelines may be greater than a width of each of the first bit lines, and awidth of each of the second connection conductive lines may be greaterthan a width of each of the second bit lines.

In an embodiment, one end portion of each of the first bit lines mayextend onto the first connection region, but another end portion of eachof the first bit lines may not extend onto the second connection region.One end portion of each of the second bit lines may extend onto thesecond connection region but another end portion of each of the secondbit lines may not extend onto the first connection region.

In an embodiment, on the first connection region, a width of one endportion of each of the first bit lines may be greater than a width of aline portion of each of the first bit lines. On the second connectionregion, a width of one end portion of each of the second bit lines maybe greater than a width of a line portion of each of the second bitlines.

In an embodiment, on the first connection region, a width of one endportion of each of the first connection conductive lines may be greaterthan a width of a line portion of each of the first connectionconductive lines. On the second connection region, a width of one endportion of each of the second connection conductive lines may be greaterthan a width of a line portion of each of the second connectionconductive lines.

In an embodiment, one of the first bit lines adjacent to each other maylaterally protrude from the other of the first bit lines adjacent toeach other on the first connection region, and one of the second bitlines adjacent to each other may laterally protrude from the other ofthe second bit lines adjacent to each other on the second connectionregion.

In an embodiment, one of the first connection conductive lines adjacentto each other may laterally protrudes from the other of the firstconnection conductive lines adjacent to each other on the firstconnection region, and one of the second connection conductive linesadjacent to each other may laterally protrude from the other of thesecond connection conductive lines adjacent to each other on the secondconnection region.

In an embodiment, the memory structure may further include asemiconductor layer, a stack structure including a plurality ofelectrodes vertically stacked on the semiconductor layer, and aplurality of active pillars penetrating the stack structure. The firstand second bit lines may be electrically connected to top ends of theactive pillars.

In an embodiment, the memory structure may further include a datastorage element disposed between each of the active pillars and theelectrodes.

In an embodiment, the stack structure includes a plurality of stackstructures spaced apart from each other in the longitudinal direction ofthe first and second bit lines. In this case, the semiconductor devicemay further include an upper insulating layer covering sidewalls of theoutermost ones of the stack structures and extending onto the first andsecond connection regions, first connection contacts disposed in theupper insulating layer of the first connection region to electricallyconnect the first bit lines to the first connection conductive lines,and second connection contacts disposed in the upper insulating layer ofthe second connection region to electrically connect the second bitlines to the second connection conductive lines.

In an embodiment, the lower insulating layer may extend onto the firstand second connection regions. In this case, the semiconductor devicemay further include first connection conductive pads disposed in thelower insulating layer of the first connection region so as to be incontact with one-end portions of the first connection contacts, andsecond connection conductive pads disposed in the lower insulating layerof the second connection region so as to be in contact with one-endportions of the second connection contacts.

In an embodiment, widths of the first connection conductive pads may begreater than widths of the first connection conductive lines, and widthsof the second connection conductive pads may be greater than widths ofthe second connection conductive lines.

In an embodiment, each of the active pillars may include verticalportions penetrating the stack structure and a horizontal portiondisposed under the stack structure to connect the vertical portions toeach other.

In an embodiment, each of the first and second bit lines may include afirst conductive material, and each of the first and second connectionconductive lines may include a second conductive material of which amelting point is higher than that of the first conductive material.

In an embodiment, the first conductive material may include copper (Cu)or aluminum (Al), and the second conductive material may includetungsten (W).

In another aspect, a semiconductor device may include a logic structureand a memory structure sequentially stacked on a substrate. The logicstructure may include a first page buffer disposed adjacently to oneside of the memory structure, and a second page buffer disposedadjacently to another side, opposite to the one side, of the memorystructure. The memory structure may include first bit lines electricallyconnected to the first page buffer, and second bit lines electricallyconnected to the second page buffer. The first bit lines and the secondbit lines may extend along a direction in which the first and secondpage buffers are opposite to each other. The first bit lines and thesecond bit lines may be alternately and repeatedly arranged along adirection intersecting the extending direction of the first and secondbit lines.

In an embodiment, the logic structure may further include firstconnection conductive lines electrically connected to first logictransistors constituting the first page buffer, and second connectionconductive lines electrically connected to second logic transistorsconstituting the second page buffer. The first connection conductivelines may overlap with the first bit lines when viewed from a plan view,and the second connection conductive lines may overlap with the secondbit lines when viewed from a plan view.

In an embodiment, the first and second bit lines may be alternately andrepeatedly arranged with a first pitch. The first connection conductivelines may have a second pitch greater than the first pitch, and thesecond connection conductive lines may have a third pitch greater thanthe first pitch.

In an embodiment, one end portion of each of the first bit lines maylaterally protrude from the one side of the memory structure, butanother end portion of each of the first bit lines may not laterallyprotrude from the another side of the memory structure. One end portionof each of the second bit lines may laterally protrude from the anotherside of the memory structure, but another end portion of each of thesecond bit lines may not laterally protrude from the one side of thememory structure.

In an embodiment, a width of the one end portion of each of the firstbit lines may be wider than a width of a line portion of each of thefirst bit lines, and a width of the one end portion of each of thesecond bit lines may be wider than a width of a line portion of each ofthe second bit lines.

In an embodiment, a protruding length, from the one side of the memorystructure, of one of the first bit lines adjacent to each other may begreater than that of the other of the first bit lines adjacent to eachother. A protruding length, from the another side of the memorystructure, of one of the second bit lines adjacent to each other may begreater than that of the other of the second bit lines adjacent to eachother.

In an embodiment, the memory structure may further include asemiconductor layer, stack structures disposed on the semiconductorlayer, and a plurality of active pillars penetrating each of the stackstructures. Each of the stack structures may include a plurality ofelectrodes vertically stacked on the semiconductor layer. The stackstructures may be spaced apart from each other in the extendingdirection of the first and second bit lines, and the first and secondbit lines may be electrically connected to top ends of the activepillars.

In an embodiment, the memory structure may further include a datastorage element disposed between each of the active pillars and theelectrodes.

In an embodiment, the semiconductor device may further include an upperinsulating layer, first connection contacts, and second connectioncontacts. The upper insulating layer may cover sidewalls of theoutermost ones of the stack structures. One of the outermost stackstructures may be adjacent to the first page buffer, and another of theoutermost stack structures may be adjacent to the second page buffer.The first connection contacts may penetrate the upper insulating layercovering the sidewall of the one outermost stack structure toelectrically connect the first bit lines to the first connectionconductive lines, and the second connection contacts may penetrate theupper insulating layer covering the sidewall of the another outermoststack structure to electrically connect the second bit lines to thesecond connection conductive lines.

In an embodiment, the semiconductor device may further include an upperinsulating layer covering sidewalls of the outermost ones of the stackstructures, first connection contacts penetrating the upper insulatinglayer covering the sidewall of one of the outermost stack structures,and second connection contacts disposed between the stack structuresadjacent to each other. The first connection contacts may constitute afirst group, and the second connection contacts may constitute a secondgroup. The first bit lines may be electrically connected to the firstconnection conductive lines through the connection contacts of one ofthe first and second groups, and the second bit lines may beelectrically connected to the second connection conductive lines throughthe connection contacts of the other of the first and second groups.

In an embodiment, one of the outermost stack structures may be adjacentto the first page buffer, and another of the outermost stack structuresmay be adjacent to the second page buffer. The first connection contactsmay penetrate the upper insulating layer covering the sidewall of theone outermost stack structure if the first bit lines are electricallyconnected to the first connection conductive lines through the firstconnection contacts. Alternatively, the first connection contacts maypenetrate the upper insulating layer covering the sidewall of theanother outermost stack structure if the second bit lines areelectrically connected to the second connection conductive lines throughthe first connection contacts.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive concepts will become more apparent in view of the attacheddrawings and accompanying detailed description.

FIG. 1 is a schematic block diagram illustrating a semiconductor memorydevice according to an embodiment of the inventive concepts.

FIG. 2 is a cross-sectional view schematically illustrating anarrangement of components of a semiconductor memory device according toan embodiment of the inventive concepts.

FIGS. 3A and 3B are plan views schematically illustrating arrangementsof components of semiconductor memory devices according to embodimentsof the inventive concepts.

FIG. 4 is a circuit diagram illustrating an embodiment of a memorystructure included in a semiconductor memory device according to anembodiment of the inventive concepts.

FIG. 5A is a plan view illustrating a semiconductor memory deviceaccording to an embodiment of the inventive concepts.

FIG. 5B is a cross-sectional view taken along line A-A′ of FIG. 5A.

FIG. 5C is a cross-sectional view corresponding to the line A-A′ of FIG.5A to illustrate a modified embodiment of a semiconductor memory deviceaccording to an embodiment of the inventive concepts.

FIGS. 6A to 12A are plan views illustrating a method of manufacturing asemiconductor memory device according to an embodiment of the inventiveconcepts.

FIGS. 6B to 12B are cross-sectional views taken along lines A-A′ ofFIGS. 6A to 12A, respectively.

FIGS. 13A to 13D are cross-sectional views taken along a direction thatintersects the bit lines of a semiconductor memory device according toan embodiment of the inventive concepts to illustrate a method offorming the bit lines.

FIG. 14A is a plan view illustrating a semiconductor memory deviceaccording to another embodiment of the inventive concepts.

FIG. 14B is a cross-sectional view taken along a line A-A′ of FIG. 14A.

FIG. 15 is a plan view illustrating a semiconductor memory deviceaccording to yet another embodiment of the inventive concepts.

FIG. 16 is a plan view illustrating a semiconductor memory deviceaccording to a further embodiment of the inventive concepts.

FIG. 17 is a circuit diagram illustrating an embodiment of a memorystructure included in a semiconductor memory device according to stillanother embodiment of the inventive concepts.

FIG. 18 is a cross-sectional view illustrating a semiconductor memorydevice according to yet another embodiment of the inventive concepts.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concepts will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the inventive concepts are shown. The advantages and features of theinventive concepts and methods of achieving them will be apparent fromthe following exemplary embodiments that will be described in moredetail with reference to the accompanying drawings. It should be noted,however, that the inventive concepts are not limited to the followingexemplary embodiments, and may be implemented in various other forms.Accordingly, the exemplary embodiments are provided only to disclose theinventive concepts and let those skilled in the art know the category ofthe inventive concepts. In the drawings, the sizes of various elementsmay be exaggerated for clarity. The same reference numerals or the samereference designators denote the same elements throughout thespecification.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit the inventive concepts. Asused herein, the singular terms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items. It will befurther understood that the terms “comprises”, “comprising,”, “includes”and/or “including”, when used herein, specify the presence of statedfeatures, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features, steps,operations, elements, components, and/or groups thereof. Similarly, itwill be understood that when an element such as a layer, region orsubstrate is referred to as being “on” another element, it can bedirectly on the other element or intervening elements may be present. Incontrast, the term “directly” means that there are no interveningelements. It will be also understood that although the terms first,second, third etc. may be used herein to describe various elements,these elements should not be limited by these terms. These terms areonly used to distinguish one element from another element. Thus, a firstelement in some embodiments could be termed a second element in otherembodiments without departing from the teachings of the inventiveconcepts.

Additionally, the exemplary embodiments in the detailed description aredescribed with reference to cross-sectional views and/or plan views thatillustrate ideal exemplary views of the inventive concepts. Accordingly,shapes of actual devices may vary from the shapes illustrated hereindue, for example, to manufacturing techniques and/or allowable errors.Therefore, the embodiments of the inventive concepts are not limited tothe specific shapes illustrated in the exemplary views, but may includeother shapes that may result from, for example, manufacturing processes.For example, an etching region illustrated as a rectangle may haverounded or curved features. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to limit thescope of example embodiments.

Hereinafter, embodiments of the inventive concepts will be described inmore detail with reference to the drawings.

FIG. 1 is a schematic block diagram illustrating a semiconductor memorydevice according to an embodiment of the inventive concepts.

Referring to FIG. 1, the semiconductor memory device may include controllogic 10 and a memory cell array 20. The control logic 10 may include arow decoder 12, a page buffer 14, a column decoder 16, and a controlcircuit 18. The memory cell array 20 may include a plurality of memoryblocks BLK0 to BLKn. Each of the memory blocks BLK0 to BLKn may includea plurality of memory cells, a plurality of word lines, and a pluralityof bit lines. The word lines and the bit lines may be electricallyconnected to the memory cells.

The row decoder 12 may decode an address signal that is input from anexternal source to select one of the word lines. The address signaldecoded in the row decoder 12 may be provided to a row driver (notshown), and the row driver may provide word line voltages generated froma voltage generating circuit (not shown) to the selected word line andunselected word lines in response to a control signal of the controlcircuit 18. The word line voltage provided to the selected word line maybe different from the word line voltages provided to the unselected wordlines. The row decoder 12 may be connected in common to the plurality ofmemory blocks BLK0 to BLKn and may provide driving signals (e.g., theword line voltages) to the word lines of a memory block (one of BLK0 toBLKn) that is selected by a block selection signal.

The page buffer 14 may be connected to the memory cell array 20 throughthe bit lines to sense data stored in the memory cells and to write datato the memory cells. The page buffer 14 may be connected to the bit lineselected by an address signal decoded from the column decoder 16. Duringa write or “program” operation, the page buffer 14 may temporarily storedata that is to be stored in the memory cells. During a read operation,the page buffer 14 may sense data that is stored in the memory cells.For example, the page buffer 14 may act as a write driver circuit duringa program operation and may act as a sense amplifier circuit during aread operation. The page buffer 14 may receive a power (e.g., a voltageor a current) from the control circuit 18 and may provide the receivedpower to the selected bit line.

The column decoder 16 may provide a data transmission path between thepage buffer 14 and an external device (e.g., a memory controller). Thecolumn decoder 16 may decode the address signal that is input from theexternal device to select one of the bit lines. The column decoder 16may be connected in common to the memory blocks BLK0 to BLKn and mayprovide data to the bit lines of the memory block (one of BLK0 to BLKn)that is selected by the block selection signal.

The control circuit 18 may control overall operations of thesemiconductor memory device. The control circuit 18 may receive controlsignals and an external voltage and may be operated in response to thereceived control signals. The control circuit 18 may include a voltagegenerator that generates voltages (e.g., a program voltage, a sensingvoltage, and/or an erasing voltage) that are necessary to internaloperations using the externally supplied voltage. The control circuit 18may perform a sensing operation, a writing operation, and/or an erasingoperation in response to the control signals.

FIG. 2 is a cross-sectional view schematically illustrating anarrangement of components of a semiconductor memory device according toan embodiment of the inventive concepts. FIGS. 3A and 3B are plan viewsschematically illustrating arrangements of components of semiconductormemory devices according to embodiments of the inventive concepts.

Referring to FIGS. 2, 3A, and 3B, a semiconductor memory device mayinclude a logic structure 10 disposed on a substrate 100, and a memorystructure 20 disposed on the logic structure 10. The logic structure 10may correspond to the control logic 10 of FIG. 1, and the memorystructure 20 may correspond to the memory cell array 20 of FIG. 1.

The substrate 100 may include a circuit region CR and a connectionregion ER that is adjacent one or more edges of the circuit region CR.The connection region ER may include first and second connection regionsER1 and ER2 that each extend parallel to a first direction D1 and thirdand fourth connection regions ER3 and ER4 that each extend perpendicularto the first direction D1 when viewed from a plan view. In other words,the third and fourth connection regions ER3 and ER4 may each extend in adirection that is be perpendicular to the directions in which the firstand second connection regions ER1 and ER2 extend when viewed from a planview. The circuit region CR may have first and second sides that areopposite each other in a second direction D2 and third and fourth sidesthat are opposite each other in the first direction D1, when viewed froma plan view. The first and second connection regions ER1 and ER2 may beadjacent the first and second sides of the circuit region CR,respectively, and the third and fourth connection regions ER3 and ER4may be adjacent the third and fourth sides of the circuit region CR,respectively. Here, the first direction D1 may correspond to a directionin which the word lines (WL0 to WL3 of FIG. 4) extend, and the seconddirection D2 may correspond to a direction in which the bit lines (BL ofFIG. 4) extend to intersect the word lines WL0 to WL3.

The logic structure 10 and the memory structure 20 may be sequentiallystacked on the circuit region CR of substrate 100. In addition, thelogic structure 10 may extend onto the connection region ER of thesubstrate 100. In other words, a portion of the row and column decoders12 and 16, the page buffer 14 and the control circuit 18 constitutingthe logic structure 10 may be disposed on the circuit region CR, andanother portion of the row and column decoders 12 and 16, the pagebuffer 14 and the control circuit 18 may be disposed on the connectionregion ER. In an embodiment, a portion of the logic structure 10 may bedisposed on both the circuit region CR and the connection region ER.

According to an embodiment of the inventive concepts, the page buffer 14of FIG. 1 may be divided into two portions. The two portions of the pagebuffer 14 may be adjacent the respective first and second sides of thecircuit region CR, and hence may be opposite each other in the seconddirection D2. In other words, the page buffer 14 may include a firstpage buffer 14_1 that is adjacent the first connection region ER1 and asecond page buffer 14_2 that is adjacent the second connection regionER2. The first and second page buffers 14_1 and 14_2 may verticallyoverlap the circuit region CR. As used herein, a first element“vertically overlaps” a second element if an imaginary line that isperpendicular to a major face of the substrate on which the elements areprovided intersects both the first element and the second element. FIGS.3A and 3B illustrate the first and second page buffers 14_1 and 14_2vertically overlapping only the circuit region CR and not the connectionregion ER. However, the inventive concepts are not limited thereto. Forexample, in other embodiments, a portion of the first page buffer 14_1may also vertically overlap the first connection region ER1, and aportion of the second page buffer 14_2 may also vertically overlap thesecond connection region ER2.

Other components of the semiconductor memory device may also bevariously arranged. For example, the control circuit 18 may be providedunderneath the circuit region CR so as to vertically overlap with thememory structure 20, as illustrated in FIG. 3A. The row and columndecoders 12 and 16 may be provided underneath the connection region ERand may not vertically overlap the memory structure 20. In theillustrated embodiments, the row decoder 12 is divided into two portionsthat are disposed underneath the third and fourth connection regions ER3and ER4, respectively, and the column decoder 16 is divided into twoportions that are disposed underneath the first and second connectionregions ER1 and ER2, respectively. In some embodiments, as illustratedin FIG. 3B, the page buffer 14, the column decoder 16, and a portion ofthe control circuit 18 may be on the circuit region CR so as tovertically overlap with the memory structure 20. In addition, the rowdecoder 12 and other portions of the control circuit 18 may be on thefirst to fourth connection regions ER1 to ER4. Meanwhile, a connectionstructure 30 may be disposed on the logic structure 10 of the connectionregion ER. However, the inventive concepts are not limited thereto. Inother embodiments, the connection structure 30 may be disposed on thecircuit region CR, unlike the embodiment illustrated in FIG. 2.

In some embodiments, bit lines that are connected to the memory cells ofthe memory structure 20 may be electrically connected to the first andsecond page buffers 14_1, 14_2. For each pair of adjacent bit lines, thefirst bit line of the pair may be connected to the first page buffer14_1, and the second bit line of the pair may be connected to the secondpage buffer 14_2. The bit lines may be arranged to satisfy theconnection relation of the two bit lines described above. As a result,since the page buffer 14 and the bit lines have the arrangement andconnection relations described above, it is possible to increase adesign rule of connection conductive lines of the logic structure 20which electrically connect the page buffer 14 to the bit lines. This isbecause the connection conductive lines are divided into respectivegroups corresponding to positions of the first and second page buffers14_1, 14_2 of the page buffer 14. This will be described in more detailbelow with reference to semiconductor memory devices according toembodiments of the inventive concepts.

In addition, the above mentioned relationships among the page buffer 14,the bit lines and the connection conductive lines that connect the pagebuffer 14 to the bit lines may be applied to other elements (e.g., wordlines, or upper interconnections formed on the memory structure 20),other logic circuits (e.g., the decoders, the control circuit, or aninput/output circuit for interfacing with an external device) connectedto the other elements, and other connection conductive lines connectingthe other elements to the other logic circuits.

Each of the memory cells of the memory structure 20 may include a chargestorage-type memory element (e.g., a flash memory device), or a variableresistance-type memory element (e.g., a phase-change random accessmemory (PRAM), a resistive random access memory (ReRAM) or a magneticrandom access memory (MRAM)). In some embodiments, the memory cells mayhave a NAND array structure. However, the inventive concepts are notlimited thereto. In other embodiment, the memory cells may have anotherarray structure (e.g., a NOR array structure or an AND array structure).

FIG. 4 is a circuit diagram illustrating an embodiment of a memorystructure that may be included in semiconductor memory devices accordingto some embodiments of the inventive concepts.

Referring to FIG. 4, the memory structure of the semiconductor memorydevice may include at least one common source line CSL, a plurality ofbit lines BL, and a plurality of cell strings CSTR that are disposedbetween the common source line CSL and the bit lines BL.

The bit lines BL may be two-dimensionally arranged. A plurality of cellstrings CSTR may be connected in parallel to each of the bit lines BL.The cell strings CSTR may be connected in common to the common sourceline CSL. In other words, cell strings CSTR may be disposed between oneof the common source lines CSL and multiple of the bit lines BL. In someembodiments, a plurality of common source lines CSL may be provided. Insuch embodiments, the common source lines CSL may be two-dimensionallyarranged. In such embodiments, the same voltage may be applied to all ofthe common source lines CSL or, alternatively, the common source linesCSL may be electrically controlled independently of each other.

Each of the cell strings CSTR may include a ground selection transistorGST that is connected to the corresponding common source line CSL, astring selection transistor SST that is connected to the correspondingbit line BL, and a plurality of memory cell transistors MCT that aredisposed between the ground and string selection transistors GST andSST. The ground selection transistor GST, the memory cell transistorsMCT, and the string selection transistor SST may be electricallyconnected in series to each other.

The common source line CSL may be connected in common to sources of theground selection transistors GST. A ground selection line GSL, aplurality of word lines WL0 to WL3 and a string selection line SSL,which are disposed between the common source line CSL and the bit linesBL, may be used as gate electrodes of the ground selection transistorGST, the memory cell transistors MCT and the string selection transistorSST, respectively. Each of the memory cell transistors MCT may include adata storage element.

FIG. 5A is a plan view illustrating a semiconductor memory deviceaccording to an embodiment of the inventive concepts. FIG. 5B is across-sectional view taken along a line A-A′ of FIG. 5A. FIG. 5C is across-sectional view corresponding to the line A-A′ of FIG. 5A thatillustrates a modified embodiment of the semiconductor memory device ofFIG. 5A.

Referring to FIGS. 5A and 5B, a substrate 100 may be provided. Thesubstrate 100 may include a circuit region CR and a connection regionthat is adjacent edges of the circuit region CR. The connection regionmay include the first connection region ER1 and the second connectionregion ER2 that are described above with reference to FIGS. 3A and 3B.In other words, the first and second connection regions ER1 and ER2 maybe provided adjacent the respective sides of the circuit region CR thatare opposite each other in the second direction D2. The third and fourthconnection regions ER3 and ER4 that are described above with referenceto FIGS. 3A and 3B are omitted from FIG. 5A to simplify the drawing andassociated description, but it will be understood that the third andfourth connection regions ER3 and ER4 may be included in thesemiconductor memory device of FIGS. 5A and 5B.

The substrate 100 may be a semiconductor substrate having a firstconductivity type (e.g., a P-type). The semiconductor substrate mayinclude, for example, at least one of a single-crystalline siliconlayer, a silicon-on-insulator (SOI), a silicon layer formed on asilicon-germanium (SiGe) layer, a single-crystalline silicon layerformed on an insulating layer, or a poly-crystalline silicon layerformed on an insulating layer.

A logic structure 10 and a memory structure 20 may be sequentiallystacked on the substrate 100. The logic structure 10 may include logiccircuits such as the row and column decoders 12 and 16 of FIG. 1, thepage buffer 14 of FIG. 1, and the control circuit 18 of FIG. 1. Thelogic circuits may be extend throughout the entire top surface of thesubstrate 100 (i.e., top surfaces of the circuit region CR and theconnection region). In some embodiments, at least the page buffer 14 maybe provided on the circuit region CR. The page buffer 14 may include thefirst page buffer 14_1 that is adjacent the first connection region ER1and the second page buffer 14_2 that is adjacent the second connectionregion ER2, as described above with reference to FIGS. 3A and 3B. Asshown in FIG. 5B, the first page buffer 14_1 may include a plurality offirst logic transistors TR1 and the second page buffer 14_2 may includea plurality of second logic transistors TR2. It will be appreciated thatonly a few representative transistors are illustrated in FIG. 5B andthat other elements of the logic structure 10 may also includetransistors and other elements that are not shown in FIG. 5B. The firstand second logic transistors TR1 and TR2 may be formed on active regionsthat are defined by a device isolation layer 102. In addition, the logicstructure 10 may further include a plurality of first connectionconductive lines L1 that are connected to the first logic transistorsTR1 and a plurality of second connection conductive lines L2 that areconnected to the second logic transistors TR2. The first connectionconductive lines L1 extend onto the first connection region ER1, and thesecond connection conductive lines L2 extend onto the second connectionregion ER2. The first and second connection conductive lines L1 and L2will be described in more detail below.

The logic structure 10 may further include lower interconnections 120,lower contacts 122, and a lower insulating layer. The lowerinterconnections 120 and the lower contacts 122 may be electricallyconnected to the logic circuits (e.g., the first and second logictransistors TR1 and TR2), and the lower insulating layer may cover thelower interconnections 120 and the lower contacts 122. The lowerinsulating layer may include first, second and third lower insulatinglayers 112, 114 and 116. However, the inventive concepts are not limitedthereto. Each of the first to third lower insulating layers 112, 114 and116 may include, for example, at least one of a silicon oxide layer, asilicon nitride layer, or a silicon oxynitride layer.

The memory structure 20 may be disposed on the third lower insulatinglayer 116 of the circuit region CR. The memory structure 20 may includea semiconductor layer 130, stack structures ST that are on thesemiconductor layer 130, and active pillars AP that penetrate the stackstructures ST.

The semiconductor layer 130 may not extend into the connection region.Consequently, portions of the third lower insulating layer 116 that arein the first and second connection regions ER1 and ER2 may be exposed bythe semiconductor layer 130. The semiconductor layer 130 may include asingle-crystalline silicon layer or a poly-crystalline silicon layer.The semiconductor layer 130 may have the first conductivity type (e.g.,a P-type). A buffer insulating layer 152 may be provided between thesemiconductor layer 130 and the stack structures ST. For example, thebuffer insulating layer 152 may include a silicon oxide layer.

The stack structures ST may include insulating patterns 155 andelectrodes that are alternately stacked on the buffer insulating layer152. The electrodes may include a ground selection line GSL, word linesWL and a string selection line SSL which are sequentially stacked on thesemiconductor layer 130 with the insulating patterns 155 therebetween.The insulating patterns 155 may include silicon oxide. The electrodesGSL, WL and SSL may include doped silicon, a metal (e.g., tungsten), ametal nitride, a metal silicide, or any combination thereof. The groundselection line GSL, the word lines WL, and the string selection line SSLmay be electrically connected to the row decoder 12 that is describedabove with reference to FIG. 1. The row decoder 12 may apply a voltageto each of the ground selection line GSL, the word lines WL and thestring selection line SSL. Nine word lines WL are illustrated in FIG.5B. However, the inventive concepts are not limited thereto. The numberof the word lines WL may be smaller or larger than nine.

One end (e.g., a bottom end) of each of the active pillars AP may bephysically and/or electrically connected to the semiconductor layer 130.The active pillars AP may be arranged in columns that extend in a firstdirection (direction D1 in FIG. 5A). In some embodiments, the activepillars AP may be arranged in a zigzag pattern when viewed from a planview. Alternatively, the active pillars AP may be arranged in rows andcolumns that form a matrix when viewed from a plan view. Each of theactive pillars AP may include a semiconductor pattern. The semiconductorpattern may include silicon or silicon-germanium which is doped withdopants of the first conductivity type. Each of the active pillars APmay have a hollow cylindrical shape (e.g., a macaroni shape), so aninner hole may be defined in each of the active pillars AP. The innerhole of each of the active pillars AP may be filled with a fillinginsulation layer 158. The filling insulation layer 158 may be, forexample, silicon oxide. A conductive pad D may be provided on a top endof each active pillar AP. The conductive pad D may be a semiconductormaterial doped with dopants or may be another conductive material.

The memory structure 20 may further include a data storage element DSdisposed between each of the active pillars AP and the electrodes GSL,WL and SSL. The data storage element DS may include a blockinginsulating layer that is adjacent the electrodes GSL, WL and SSL, atunnel insulating layer that is adjacent the active pillar AP, and acharge storage layer that is between the blocking insulating layer andthe tunnel insulating layer.

The blocking insulating layer may include a hafnium oxide layer, analuminum oxide layer, and/or a silicon oxide layer. A stacking order ofthe hafnium oxide layer, the aluminum oxide layer and/or the siliconoxide layer may be variously modified. The tunnel insulating layer mayinclude silicon oxide. The charge storage layer may include a chargetrap layer or an insulating layer including conductive nano particles.The charge trap layer may include, for example, silicon nitride. Datastored in the data storage layer DS may be changed using Fowler-Nordheimtunneling that occurs in response to application of a voltagedifferential between the active pillar AP including the semiconductorpattern and the electrodes. Alternatively, the data storage element DSmay include a thin layer capable of storing data based on anotheroperating principle, e.g., a thin layer for a phase-change memory or athin layer for a variable resistance memory.

A plurality of stack structures ST may be provided. Each stack structureST may extend in the first direction D1 and the stack structures ST maybe spaced apart from each other in a second direction D2 that intersects(e.g., is perpendicular to) the first direction D1. Common sourceregions 170 may be provided in the semiconductor layer 130 betweenadjacent ones of the stack structures ST. Each common source region 170may extend in the first direction D1. The common source regions 170 mayhave a second conductivity type (e.g., an N-type). Common source plugs173 may be provided between adjacent stack structures ST and may connectto respective ones of the common source regions 170. An isolationinsulating layer 175 may be provided on either side of each commonsource plug 173 to isolate each common source plug from the stackstructures ST adjacent thereto. A ground voltage may be applied to thecommon source regions 170 through the common source plugs 173 during asensing or program operation of the semiconductor memory device. In someembodiments, each common source plug 173 may extend in the firstdirection D1 and may have a substantially uniform upper width in thesecond direction. In such embodiments, the isolation insulating layer175 may have a spacer shape and may be on a sidewall of each of thestack structures ST. In other words, the isolation insulating layers 175that are provided between adjacent stack structures ST may face eachother with the common source plug 173 therebetween. In otherembodiments, the isolation insulating layer 175 may fill a space betweenadjacent stack structures ST, and the common source plug 173 (or aplurality of common source plugs 173) may have a pillar shape and maypenetrate the isolation insulating layer 175 so as to be locallyconnected to the common source region 170.

A first upper insulating layer 140 may be provided on the first andsecond connection regions ER1 and ER2 to cover a sidewall of thesemiconductor layer 130 and an exposed top surface of the third lowerinsulating layer 116. A second upper insulating layer 160 may beprovided on the first upper insulating layer 140 to cover outersidewalls of the stack structures ST. While not shown in the drawings,end portions of the electrodes GSL, WL and SSL of the stack structure STmay have a stepped structure.

A third upper insulating layer 180 may be provided on the stackstructures ST and the second upper insulating layer 160, and a fourthupper insulating layer 190 may be provided on the third upper insulatinglayer 180. Bit line contacts 185 may penetrate the third upperinsulating layer 180. Bit lines BL may be provided in the fourth upperinsulating layer 190. The bit lines BL may be electrically connected tothe active pillars AP through the bit line contacts 185 and theconductive pads D. Each of the first to fourth upper insulating layers140, 160, 180 and 190 may include at least one of a silicon oxide layer,a silicon nitride layer, or a silicon oxynitride layer.

According to an embodiment of the inventive concepts, a first pair ofadjacent bit lines BL may be electrically connected to the first pagebuffer 14_1, and a second pair of adjacent bit lines BL may beelectrically connected to the second page buffer 14_2. In other words,the bit lines BL may be arranged in pairs where each pair includes afirst bit line BL1 and a second bit line BL2 that are adjacent eachother. The first bit lines BL1 are electrically connected to the firstpage buffer 14_1 and the second bit lines BL2 are electrically connectedto the second page buffer 14_2. The bit lines BL may be configured suchthat the first bit lines BL1 and the second bit lines BL2 arealternately and repeatedly arranged along the first direction D1.

End portions of the first bit lines BL1 may extend onto the firstconnection region ER1 and may or may not extend onto the secondconnection region ER2. The first bit lines BL1 may be electricallyconnected to the first logic transistors TR1 of the first page buffer14_1 through first connection contacts C1 and the first connectionconductive lines L1. On the first connection region ER1, each of thefirst connection conductive lines L1 may vertically overlap acorresponding one of the first bit lines BL1. The first connectioncontacts C1 may be disposed on the first connection region ER1 and maypenetrate the first to third upper insulating layers 140, 160 and 180and the second and third lower insulating layers 114 and 116. In someembodiments, first ends of the first connection contacts C1 may directlycontact respective ones of the first bit lines BL1, and second ends ofthe first connection contacts C1 may directly contact respective ones ofthe first connection conductive lines L1.

Likewise, end portions of the second bit lines BL2 may extend onto thesecond connection region ER2 and may or may not extend onto the firstconnection region ER1. The second bit lines BL2 may be electricallyconnected to the second logic transistors TR2 of the second page buffer14_2 through second connection contacts C2 and the second connectionconductive lines L2. On the second connection region ER2, each of thesecond connection conductive lines L2 may vertically overlap acorresponding one of the second bit lines BL2. The second connectioncontacts C2 may be disposed on the second connection region ER2 and maypenetrate the first to third upper insulating layers 140, 160 and 180and the second and third lower insulating layers 114 and 116. In someembodiments, first ends of the second connection contacts C2 maydirectly contact respective ones of the second bit lines BL2, and secondends of the second connection contacts C2 may directly contactrespective ones of the second connection conductive lines L2. Theconnection structure 30 described with reference to FIGS. 2, 3A and 3Bmay include the first and second connection contacts C1 and C2.

The bit lines BL may have substantially the same width and may be spacedapart from each other by substantially equal distances. For example,each of the bit lines BL may have a first width w1, and adjacent bitlines BL may be spaced apart from each other by a first distance d1. Inother words, the bit lines BL may have a first pitch defined as a sum ofthe first width w1 and the first distance d1. First end portions of thebit lines BL may be aligned with each other along the first direction D1on the first connection region ER1, and second end portions of the bitlines BL may be aligned with each other along the first direction D1 onthe second connection region ER2. In the present embodiment, both endportions (i.e., the first and second end portions) of each of the bitlines BL may extend onto the first and second connection regions ER1 andER2, respectively. However, the inventive concepts are not limitedthereto. In other embodiments, one end portion of each of the first bitlines BL1 may not extend onto the first connection region ER1, and/orone end portion of each of the second bit lines BL2 may not extend ontothe second connection region ER2. For example, as shown in FIG. 5C, inanother example embodiment one end portion (the left end portion) ofeach of the second bit lines BL2 may extend onto the first connectionregion ER1, but the other end portion of each of the second bit linesBL2 may not extend onto the second connection region ER2. In such anembodiment, the second connection conductive lines L2 may not extendonto the second connection region ER2. In this case, the second bitlines BL2 may be electrically connected to the second connectionconductive lines L2 through second connection contacts C2 that penetratethe isolation insulating layer 175 that is disposed between adjacentstack structures ST. In other words, the second connection contacts C2may penetrate the third upper insulating layer 180, the isolationinsulating layer 175, the semiconductor layer 130, the third lowerinsulating layer 116, and the second lower insulating layer 114 on thecircuit region CR. Even though not shown in the drawings, if one endportion of each of the first bit lines BL1 extends onto the secondconnection region ER2 but the other end portion of each of the first bitlines BL1 does not extend onto the first connection region ER1, thefirst bit lines BL1 may be electrically connected to the firstconnection conductive lines L1 through first connection contacts C1 thatare disposed between adjacent stack structures ST.

Referring again to FIGS. 5A and 5B, according to embodiments of theinventive concepts, a second distance d2 between adjacent ones of thefirst connection conductive lines L1 may be greater than the firstdistance d1 between adjacent ones of the bit lines BL. Likewise, a thirddistance d3 between adjacent ones of the second connection conductivelines L2 may be greater than the first distance d1 between adjacent onesof the bit lines BL. For example, each of the second and third distancesd2 and d3 may be substantially equal to twice the first distance d1. Insome embodiments, the second distance d2 may be substantially equal tothe third distance d3. However, the inventive concepts are not limitedthereto.

A width of each of the first and second connection conductive lines L1and L2 may be greater than the first width w1 of the bit lines BL. Inother words, each of the first connection conductive lines L1 may have asecond width w2 that is greater than the first width w1, and each of thesecond connection conductive lines L2 may have a third width w3 that isgreater than the first width w1. In some embodiments, each of the secondand third widths w2 and w3 may be substantially equal to twice the firstwidth w1. In other embodiments, each of the second and third widths w2and w3 may be greater than twice the first width w1 and less than threetimes the first width w1. In some embodiments, the second width w2 maybe substantially equal to the third width w3. However, the inventiveconcepts are not limited thereto. As a result, a second pitch of thefirst connection conductive lines L1 may be greater than the first pitchof the bit lines BL, and a third pitch of the second connectionconductive lines L2 may be greater than the first pitch of the bit linesBL. In some embodiments, the second pitch may be substantially equal tothe third pitch. Here, the second pitch of the first connectionconductive lines L1 may be defined as a sum of the second width w2 andthe second distance d2, and the third pitch may be defined as a sum ofthe third width w3 and the third distance d3.

It will also be appreciated the first and second bit lines BL1, BL2and/or the first and second connection conductive lines L1, L2 need nothave constant widths, as will be described in greater detail below. Insuch cases, an average width of one or more of the first connectionconductive lines L1 may be greater than an average width of one or moreof the first bit lines BL1, and/or an average width of one or more ofthe second connection conductive lines L2 may be greater than an averagewidth of one or more of the second bit lines BL2. For bit lines (orconnection conductive lines) that comprise multiple segments, where eachsegment has a constant width, the average width may be determined as thesum of the width of each segment multiplied by the length of thesegment, which total is then divided by the number of segments. Forexample, if the bit line has a widened area at either end thereof thathas a width of 3 microns, where each widened area is 2 microns inlength, and a line portion connecting the two widened end portions,where the line portion has a width of 1 micron and a length of 20microns, the average width for the bit line would be[(3*2)+(1*20)+(3*2)1/24=32/24=1.33.

The connection conductive lines L1 and L2 may have a physical propertycapable of preventing a process defect (e.g., a hillock defect) at themaximum temperature (hereinafter, referred to as “a process criticaltemperature”) of processes for forming the memory structure 20 and/orthe bit lines BL. In other word, the connection conductive lines L1 andL2 may be formed of conductive material(s) having a heat-resistanceproperty at the process critical temperature. For example, theconnection conductive lines L1 and L2 may include at least one material(e.g., tungsten) having a melting point that is higher than the processcritical temperature. A resistivity of the conductive material of thebit lines BL may be lower than that of the conductive material of theconnection conductive lines L1 and L2. For example, the conductivematerial of the bit lines BL may include a low resistivity material(e.g., copper or aluminum) that may cause the process defect at atemperature lower than the process critical temperature. Since the bitlines BL are formed after the memory structure 20, a low resistivitymaterial having a low melting point may be used as the conductivematerial of the bit lines BL. The resistivity of the connectionconductive lines L1 and L2 may be higher than that of the bit lines BLdue to the above mentioned limitations of the manufacturing process.This may cause deterioration of electrical characteristics of thesemiconductor memory device. However, according to embodiments of theinventive concepts, the page buffer 14 may be divided into the first andsecond page buffers 14_1 and 14_2 that are adjacent both sides of thememory structure 20, and thus it is possible to increase the widths ofthe connection conductive lines L1 and L2 that connect the bit lines BLto the page buffer 14. As a result, the resistance characteristics ofthe connection conductive lines L1 and L2 may be improved to improve theelectrical characteristics of the semiconductor memory device.

In addition, since the widths of the connection conductive lines L1 andL2 are increased, it is possible to more easily arrange and form theconnection contacts C1 and C2 that electrically connect the connectionconductive lines L1 and L2 to the bit lines BL. As a result, it ispossible to more easily realize a highly integrated semiconductor memorydevice.

A method of manufacturing a semiconductor memory device according to anembodiment of the inventive concepts will be described hereinafter.FIGS. 6A to 12A are plan views illustrating a method of manufacturingthe semiconductor memory device. FIGS. 6B to 12B are cross-sectionalviews taken along lines A-A′ of FIGS. 6A to 12A, respectively.

Referring to FIGS. 6A and 6B, a substrate 100 including a circuit regionCR and a connection region may be provided. The connection region mayinclude a first connection region ER1 and a second connection region ER2which are provided on opposed sides of the circuit region CR. Thesubstrate 100 may be a semiconductor substrate having a firstconductivity type (e.g., a P-type). The semiconductor substrate 100 mayinclude at least one of a single-crystalline silicon layer, asilicon-on-insulator (SOI), a silicon layer formed on asilicon-germanium (SiGe) layer, a single-crystalline silicon layerformed on an insulating layer, or a poly-crystalline silicon layerformed on an insulating layer.

A logic structure 10 may be formed on the substrate 100. The logicstructure 10 may include a plurality of logic transistors that form alogic circuit. The logic transistors may be formed on active regions inthe substrate 100 that are defined by a device isolation layer 102. Onthe circuit region CR, the logic transistors may include first logictransistors TR1 constituting a first page buffer 14_1 and second logictransistors TR2 constituting a second page buffer 14_2. The first logictransistors TR1 may be adjacent the first connection region ER1, and thesecond logic transistors TR2 may be adjacent the second connectionregion ER2. A lower insulating layer may be formed on the substrate 100to cover the logic transistors. The lower insulating layer may includefirst, second and third lower insulating layers 112, 114 and 116. Eachof the first to third lower insulating layers 112, 114 and 116 mayinclude at least one of a silicon oxide layer, a silicon nitride layer,or a silicon oxynitride layer.

Lower interconnections 120 and lower contacts 122 may be formed in thelower insulating layer that are connected to the logic transistors TR1,TR2. In addition, first connection conductive lines L1 and secondconnection conductive lines L2 may be formed in the lower insulatinglayer. The first connection conductive lines L1 may be electricallyconnected to the first logic transistors TR1, and the second connectionconductive lines L2 may be electrically connected to the second logictransistors TR2. The first connection conductive lines L1 may extendonto the first connection region ER1, and the second connectionconductive lines L2 may extend onto the second connection region ER2.Each of the first connection conductive lines L1 may have a second widthw2, and adjacent ones of the first connection conductive lines L1 may bespaced apart from each other by a second distance d2. Each of the secondconnection conductive lines L2 may have a third width w3, and adjacentones of the second connection conductive lines L2 may be spaced apartfrom each other by a third distance d3. The first connection conductivelines L1 and the second connection conductive lines L2 may be arrangedin patterns having pitches that are equal to or greater than the minimumpitch realized by a photolithography process. In other word, the firstand second connection conductive lines L1 and L2 may be formed using asingle-patterning technique. For example, a conductive layer may beformed on the first lower insulating layer 112, and the conductive layermay be patterned to form the first and second connection conductivelines L1 and L2. The conductive layer may include, for example,tungsten. In the present embodiment, the first and second connectionconductive lines L1 and L2 are formed on the first lower insulatinglayer 112. However, embodiments of the inventive concepts are notlimited thereto.

Referring to FIGS. 7A and 7B, a semiconductor layer 130 may be formed onthe third lower insulating layer 116. In some embodiments, thesemiconductor layer 130 may comprise a silicon epitaxial layer and mayhave a single-crystalline structure. In such embodiments, a contact hole(not shown) may be formed that penetrates the first to third lowerinsulating layers 112, 114 and 116. The contact hole may expose thesubstrate 100. The semiconductor layer 130 may be formed to fill thecontact hole and to cover the third lower insulating layer 116 by aselective epitaxial growth (SEG) method or a solid phase epitaxial (SPE)method. Thereafter, the semiconductor layer 130 disposed in the contacthole may be removed, and then the contact hole may be filled with aninsulating layer. In some embodiments, the semiconductor layer 130 maybe a poly-crystalline silicon layer. The semiconductor layer 130disposed on the first and second connection regions ER1 and ER2 may beremoved to expose the third lower insulating layer 116. Next, a firstupper insulating layer 140 may be formed on the third lower insulatinglayer 116 of the first and second connection regions ER1 and ER2 so asto cover sidewalls of the semiconductor layer 130.

Referring to FIGS. 8A and 8B, a buffer insulating layer 152 may beformed on the semiconductor layer 130 and on the first upper insulatinglayer 140. For example, the buffer insulating layer 152 may include asilicon oxide layer. The buffer insulating layer 152 may be formed by,for example, a thermal oxidation process. A thin-layer structure 150 maybe formed on the buffer insulating layer 152. The thin-layer structure150 may include sacrificial layers 153 and insulating layers 154 whichare alternately stacked on the buffer insulating layer 152. Each of theinsulating layers 154 may include, for example, a silicon oxide layer.The sacrificial layers 153 may include a material having a wet etchingcharacteristic that is different from the wet etching characteristics ofthe buffer insulating layer 152 and the insulating layers 154. Each ofthe sacrificial layers 153 may include, for example, a silicon nitridelayer, a silicon oxynitride layer, a poly-crystalline silicon layer, ora poly-crystalline silicon-germanium layer. Each of the sacrificiallayers 153 and insulating layers 154 may be formed by, for example, achemical vapor deposition (CVD) method.

Referring to FIGS. 9A and 9B, vertical holes may be formed to penetratethe thin-layer structure 150 on the circuit region CR. The verticalholes may expose the semiconductor layer 130. Active pillars AP may beformed in the respective vertical holes. One end of each of the activepillars AP may be connected to the semiconductor layer 130. Each of theactive pillars AP may include a semiconductor pattern. The semiconductorpattern may include silicon or silicon-germanium, which is doped withdopants of the first conductivity type. Each of the active pillars APmay have a hollow cylindrical shape (e.g., a macaroni shape), so aninner hole may be defined in each of the active pillars AP. The innerhole of each of the active pillars AP may be filled with a fillinginsulation layer 158. The insulating layers 154 and the sacrificiallayers 153 disposed on the first and second connection regions ER1 andER2 may be removed. Sidewalls of the insulating layers 154 andsacrificial layers 153 that are adjacent the first and second connectionregions ER1 and ER2 are vertically aligned with each other in FIGS. 9Aand 9B for the purpose of ease and convenience in illumination. However,the inventive concepts are not limited thereto. In particular, endportions of the insulating layers 154 and sacrificial layers 153 mayhave a stepped structure. A second upper insulating layer 160 may beformed on the first and second connection regions ER1 and ER2 to coverthe sidewalls of the insulating layers 154 and sacrificial layers 153.

In the above descriptions, the semiconductor layer 130 was previouslyetched in the process described with reference to FIGS. 7A and 7B.However, the inventive concepts are not limited thereto. In otherembodiments, the semiconductor layer 130 may be etched when theinsulating layers 154 and the sacrificial layers 153 of the first andsecond connection regions ER1 and ER2 are removed. In this case, thefirst upper insulating layer 140 may be omitted, and the second upperinsulating layer 160 may also cover the sidewalls of the semiconductorlayer 130.

Referring to FIGS. 10A and 10B, the thin-layer structure 150 may bepatterned to form trenches 165 that extend in the first direction D1.The trenches 165 may expose the semiconductor layer 130. The trenches165 may divide the thin-layer structure 150 into segments that areseparated from each other in the second direction D2. The patternedinsulating layers 154 may be defined as insulating patterns 155.

The sacrificial layers 153 that are exposed by the trenches 165 may beselectively removed to form recess regions RS. The recess regions RS maycorrespond to empty regions that are formed by the removal of thesacrificial layers 153 and may be defined by the active pillars AP andthe insulating patterns 155. If the sacrificial layers 153 includesilicon nitride layers or silicon oxynitride layers, the sacrificiallayers 153 may be removed using an etching solution including phosphoricacid.

Referring to FIGS. 11A and 11B, a data storage element DS may be formedin each recess region RS through the trenches 165. The data storageelement DS may include a blocking insulating layer, a tunnel insulatinglayer, and a charge storage layer that is disposed between the blockinginsulating layer and the tunnel insulating layer. A conductive layer(not shown) may be formed to fill the recess regions RS having the datastorage element DS. The conductive layer may be formed of at least oneof a doped poly-crystalline silicon layer, a metal layer (e.g., atungsten layer), or a metal nitride layer. In an embodiment, theconductive layer may include a metal nitride layer and a metal layerdisposed on the metal nitride layer. The conductive layer may be formedby, for example, an atomic layer deposition (ALD) method. At least aportion of the data storage element DS may be formed on sidewalls of thevertical holes before the formation of the active pillars AP in theprocess described with reference to FIGS. 9A and 9B.

Next, portions of the conductive layer that are outside the recessregions RS (e.g., in the trenches 165) may be removed to form electrodesGSL, WL and SSL in the respective recess regions RS and to expose thesemiconductor layer 130. The insulating patterns 155 and the electrodesGSL, WL and SSL may constitute a stack structure ST. Dopant ions of asecond conductivity type may be implanted into the exposed semiconductorlayer 130 to form common source regions 170. Conductive pads D may beformed on top end portions of the active pillars AP.

Referring to FIGS. 12A and 12B, common source plugs 173 may be formed inthe trenches 165. The common source plugs 173 may include a metal (e.g.,tungsten, copper, or aluminum). The common source plugs 173 may beelectrically connected to the common source regions 170. One or moreisolation insulating layers 175 may be formed between the common sourceplug 173 and inner sidewalls of the trench 165.

A third upper insulating layer 180 may be formed on the stack structuresST and the second upper insulating layer 160. Bit line contacts 185 maybe formed to penetrate the third upper insulating layer 180 toelectrically connect to the respective active pillars AP.

First connection contacts C1 may be formed on the first connectionregion ER1. The first connection contacts C1 may penetrate the thirdupper insulating layer 180, the second upper insulating layer 160, thefirst upper insulating layer 140, the third lower insulating layer 116,and the second lower insulating layer 114 to connect to the firstconnection conductive lines L1 on the first connection region ER1.Second connection contacts C2 may be formed on the second connectionregion ER2. The second connection contacts C2 may penetrate the thirdupper insulating layer 180, the second upper insulating layer 160, thefirst upper insulating layer 140, the third lower insulating layer 116,and the second lower insulating layer 114 to connect to the secondconnection conductive lines L2 on the second connection region ER2.

Referring again to FIGS. 5A and 5B, a fourth upper insulating layer 190may be formed on the third upper insulating layer 180. Bit lines BL maybe formed in the fourth upper insulating layer 190. First and second endportions of each of the bit lines BL may extend onto the first andsecond connection regions ER1 and ER2, respectively. A first of a pairof adjacent bit lines BL may be connected to the first connectioncontact C1, and the second of the pair of adjacent bit lines BL may beconnected to the second connection contact C2. In other words, the bitlines BL may include first bit lines BL1 that are connected to the firstpage buffer 14_1 through the first connection contacts C1 and the firstconnection conductive lines L1, and second bit lines BL2 that areconnected to the second page buffer 14_2 through the second connectioncontacts C2 and the second connection conductive lines L2. Each of thebit lines BL may have a first width w1, and adjacent bit lines BL may bespaced apart from each other by a first distance d1. The bit lines BLmay be formed to have a pitch smaller than the minimum pitch realized bya photolithography process. To achieve this, the bit lines BL may beformed using a double-pattering technique. In an embodiment, grooves maybe formed in the fourth upper insulating layer 190, and the bit lines BLmay be formed in the grooves, respectively. The grooves in the fourthupper insulating layer 190 may be formed using the double-patterningtechnique. The bit lines BL may include a conductive material (e.g.,copper or aluminum).

Hereinafter, the method of forming the bit lines BL will be described inmore detail with reference to FIGS. 13A to 13D. FIGS. 13A to 13D arecross-sectional views taken along a direction intersecting the bit linesto illustrate a method of forming the bit lines.

Referring to FIG. 13A, the fourth upper insulating layer 190 may beformed on the third upper insulating layer 180, and a hard mask layermay be formed on the fourth upper insulating layer 190. In someembodiments, the hard mask layer may include a first mask layer 60disposed on the fourth upper insulating layer 190 and a second masklayer 50 disposed between the fourth upper insulating layer 190 and thefirst mask layer 60. The second mask layer 50 may be formed of amaterial having an etch selectivity with respect to the fourth upperinsulating layer 190. For example, the second mask layer 50 may includepoly-silicon. The first mask layer 60 may be formed of a material havingan etch selectivity with respect to the second mask layer 50. Forexample, the first mask layer 60 may include an amorphous carbon layer(ACL). Although not shown, the first mask layer 60 may further include asilicon-containing material (e.g., SiON). In the present embodiment, thehard mask layer may have a double-layered structure. However, theinventive concepts are not limited thereto.

Sacrificial patterns 70 may be formed on the first mask layer 60. Insome embodiments, a sacrificial layer may be formed on the first masklayer 60 and a patterning process may be performed on the sacrificiallayer to form the sacrificial patterns 70. For example, the sacrificiallayer may include a spin-on-hardmask (SOH) layer. Each of thesacrificial patterns 70 may have a line shape extending in the seconddirection D2. The sacrificial patterns 70 may be spaced apart from eachother in a first direction D1 that is perpendicular to the seconddirection D2. The sacrificial patterns 70 may have substantially thesame width a1 and may be spaced apart from each other by a distance a2.In other words, the sacrificial patterns 70 may have a pitch defined asa sum of the width a1 and the distance a2. The distance a2 between thesacrificial patterns 70 may be greater than the width a1 of thesacrificial patterns 70. The pitch of the sacrificial patterns 70 may,for example, correspond to the minimum pitch realized by aphotolithography process.

Spacers 75 may be formed on sidewalls of the sacrificial patterns 70. Insome embodiments, the spacers 75 may be formed by forming a spacer layeron the fourth upper insulating layer 190 to conformally cover thesacrificial patterns 70, and then performing a blanket anisotropicetching process on the spacer layer until the first mask layer 60 isexposed to form the spacers 75. The spacer layer may include, forexample, a silicon oxide layer. The spacer layer may be formed by anatomic layer deposition (ALD) process. In an embodiment, a width a3 ofeach of the spacers 75 may correspond to about a third of the distancea2 between the sacrificial patterns 70. However, the inventive conceptsare not limited thereto.

Referring to FIG. 13B, the sacrificial patterns 70 may be removed. Insome embodiments, the sacrificial patterns 70 may be removed by anetching process that uses an etch recipe that has etch selectivity withrespect to the spacers 75 and the first mask layer 60. Subsequently, thefirst mask layer 60 may be etched using the spacers 75 as etch masks toform first mask patterns 60 a . A distance between the first maskpatterns 60 a may be substantially equal to the width al of thesacrificial patterns 70.

Referring to FIG. 13C, the second mask layer 50 may be etched using thefirst mask patterns 60 a as etch masks to form second mask patterns 50 a. The second mask patterns 50 a may have the substantially same shapesas the first mask patterns 60 a when viewed from a plan view. Thespacers 75 may be removed during the etching process for forming thesecond mask patterns 50 a . Alternatively, the spacers 75 may be removedbefore the formation of the second mask patterns 50 a . The first andsecond mask patterns 60 a and 50 a may expose the fourth upperinsulating layer 190.

Referring to FIG. 13D, the fourth upper insulating layer 190 may beetched using the first and second mask patterns 60 a and 50 a as etchmasks to form grooves 192 in the fourth upper insulating layer 190.Subsequently, the first and second mask patterns 60 a and 50 a may beremoved. Thereafter, the grooves 192 may be filled with a conductivematerial (e.g., copper or aluminum), thereby forming the bit lines BL.Thus, it is possible to form the bit lines BL having a pitch smallerthan the minimum pitch realized by the photolithography process.

Since the bit lines BL are formed using the double-patterning techniquedescribed above, processes of manufacturing the semiconductor memorydevice may be complex. On the contrary, the connection conductive linesthat are connected to the bit lines BL may be divided into the firstconnection conductive lines L1 and the second connection conductivelines L2, so design rules for the formation of the first and secondconnection conductive lines L1 and L2 may be increased. As a result, theconnection conductive lines L1 and L2 may be more easily formed and maynot require a more expensive photolithography apparatus and/or a complexdouble-patterning technique. Thus, the processes of manufacturing thesemiconductor memory device may be simplified and a manufacturing costof the semiconductor memory device may be reduced.

FIG. 14A is a plan view illustrating a semiconductor memory deviceaccording to another embodiment of the inventive concepts. FIG. 14B is across-sectional view taken along a line A-A′ of FIG. 14A. In the presentembodiment, the same elements as described in the above embodiments willbe indicated by the same reference numerals or the same referencedesignators, and descriptions of these elements will only be mentionedbriefly or may be omitted altogether.

Referring to FIGS. 14A and 14B, the semiconductor memory device of thepresent embodiment may further include connection conductive pads thatare provided on the second lower insulating layer 114. The connectionconductive pads may include first connection conductive pads P1 that areprovided on the first connection region ER1, and second connectionconductive pads P2 that are provided on the second connection regionER2. The first connection contacts C1 may directly contact the firstconnection conductive pads P1, and the second connection contacts C2 maydirectly contact the second connection conductive pads P2. A width w4 ofeach of the first and second connection conductive pads P1 and P2 may begreater than the width w1 of the bit lines BL and the widths w2 and w3of the connection conductive lines L1 and L2. Since the connectionconductive pads P1 and P2 having the relatively large widths are formedbetween the bit lines BL and the connection conductive lines L1 and L2,alignment margins for the connection contacts C1 and C2 may be improvedand defects (e.g., a bridge defect) that are caused by misalignment maybe reduced or prevented.

First lower connection contacts 124 a may be disposed in the secondlower insulating layer 114 of the first connection region ER1 toelectrically connect the first connection conductive pads P1 to thefirst connection conductive lines L1. Second lower connection contacts124 b may be disposed in the second lower insulating layer 114 of thesecond connection region ER2 to electrically connect the secondconnection conductive pads P2 to the second connection conductive linesL2. Other elements of the semiconductor memory device according to thepresent embodiment may be the same as or similar to correspondingelements of the semiconductor memory device described with reference toFIGS. 5A and 5B.

FIG. 15 is a plan view illustrating a semiconductor memory deviceaccording to still another embodiment of the inventive concepts. Eventhough not shown in the drawings, a cross-sectional view correspondingto a line A-A′ of FIG. 15 may be the same as or similar to FIG. 5B. Inthe present embodiment, the same elements as described in the aboveembodiments will be indicated by the same reference numerals or the samereference designators, and descriptions of these elements will only bementioned briefly or may be omitted altogether.

Referring to FIG. 15, first end portions of the first bit lines BL1 mayextend onto the first connection region ER1, but second end portions ofthe first bit lines BL1 may not extend onto the second connection regionER2. On the first connection region ER1, a width of the first endportion of each of the first bit lines BL1 may be greater than the firstwidth w1 of a line portion of each of the first bit lines BL1.Similarly, first end portions of the second bit lines BL2 may not extendonto the first connection region ER1, but second end portions of thesecond bit lines BL2 may extend onto the second connection region ER2.On the second connection region ER2, a width of the second end portionof each of the second bit lines BL2 may be greater than the first widthw1 of a line portion of each of the second bit lines BL2.

On the first connection region ER1, shapes of the first connectionconductive lines L1 may correspond to the shapes of the first bit linesBL1. In other words, a width of an end portion of each of the firstconnection conductive lines L1 may be greater than the second width w2of a line portion of each of the first connection conductive lines L1.Likewise, on the second connection region ER2, shapes of the secondconnection conductive lines L2 may correspond to the shapes of thesecond bit lines BL2. In other words, a width of an end portion of eachof the second connection conductive lines L2 may be greater than thethird width w3 of a line portion of each of the second connectionconductive lines L2. Thus, the alignment margins of the connectioncontacts C1 and C2 may be improved without additional connectionconductive pads P1 and P2. Other elements of the semiconductor memorydevice according to the present embodiment may be the same as or similarto corresponding elements of the semiconductor memory device describedwith reference to FIGS. 5A and 5B.

FIG. 16 is a plan view illustrating a semiconductor memory deviceaccording to yet another embodiment of the inventive concepts. Eventhough not shown in the drawings, a cross-sectional view correspondingto a line A-A′ of FIG. 16 may be the same as or similar to FIG. 5B. Thesemiconductor memory device of FIG. 16 may be the substantially same asor similar to the semiconductor memory device of FIG. 15, except thatpositions of end portions of some of the bit lines BL are different fromthose of end portions of others of the bit lines BL on each of theconnection regions. In the present embodiment, descriptions of the sameelements as in the above embodiments may only be mentioned briefly ormay be omitted altogether.

Referring to FIG. 16, on the first connection region ER1, positions(e.g., coordinates in the second direction D2) of end portions ofadjacent ones of the first bit lines BL1 may be different from eachother. End portions of the first bit lines BL1 may protrude from thecircuit region CR in a direction opposite to the second direction D2when viewed from a plan view. The protruding lengths of the end portionsof adjacent ones of the first bit lines BL1 may be different from eachother. In other words, the protruding length of a first of a pair ofadjacent first bit lines BL1 may be greater than the protruding lengthof the second of the pair of adjacent first bit lines BL1. The first bitlines BL1 may be repeatedly arranged along the first direction D1 insuch a way to satisfy the above mentioned positional relationship.

Likewise, on the second connection region ER2, positions (e.g.,coordinates in the second direction D2) of end portions of adjacent onesof the second bit lines BL2 may be different from each other. Endportions of the second bit lines BL2 may protrude from the circuitregion CR in the second direction D2 when viewed from a plan view. Theprotruding lengths of the end portions of adjacent ones of the secondbit lines BL2 may be different from each other. In other words, theprotruding length of a first of a pair of adjacent second bit lines BL2may be greater than the protruding length of the second of the pair ofadjacent second bit lines BL2. The second bit lines BL2 may berepeatedly arranged along the first direction D1 in such a way tosatisfy the above mentioned positional relationship. Since the first andsecond bit lines BL1 and BL2 have the positional relationships asdescribed above, it is possible to increase a distance between the endportions of adjacent ones of the first bit lines BL1 on the firstconnection region ER1 and a distance between the end portions ofadjacent ones of the second bit lines BL2 on the second connectionregion ER2. As a result, widths of the end portions of the first andsecond bit lines BL1 and BL2 may be increased to more easily form theconnection contacts C1 and C2. Shapes of the first connection conductivelines L1 may correspond to the shapes of the first bit lines BL1 on thefirst connection region ER1. In other words, protruding lengths ofadjacent ones of the first connection conductive lines L1 may bedifferent from each other when viewed from a plan view. Likewise, shapesof the second connection conductive lines L2 may correspond to theshapes of the second bit lines BL2 on the second connection region ER2.In other words, protruding lengths of adjacent ones of the secondconnection conductive lines L2 may be different from each other whenviewed from a plan view.

FIG. 17 is a circuit diagram illustrating an embodiment of a memorystructure included in a semiconductor memory device according to anembodiment of the inventive concepts.

Referring to FIG. 17, a memory structure 20 according to the presentembodiment may include a common source line CSL, a plurality of bitlines BL, and a cell string CSTR between the common source line CSL andthe bit lines BL.

The common source line CSL may be a conductive layer disposed on asubstrate, and the bit lines BL may be conductive patterns (e.g., metallines) disposed on the substrate.

The cell string CSTR may include a plurality of upper strings CSTR1respectively connected to the bit lines BL and one lower string CSTR2connected to the common source line CSL. The plurality of upper stringsCSTR1 may be connected in common to the one lower string CSTR2. Each ofthe upper strings CSTR1 may be connected to the lower string CSTR2through a respective switching element SW. The switching elements SWconnected to the upper strings CSTR1 may be electrically controlled toreceive the same voltage.

Each of the upper strings CSTR1 may include a string selectiontransistor SST connected to each of the bit lines BL, and a plurality ofupper memory cell transistors MCT1 that are disposed between the stringselection transistor SST and the switching element SW. The stringselection transistor SST and the upper memory cell transistors MCT1 maybe connected in series to each other. The lower string CSTR2 may includea ground selection transistor GST connected to the common source lineCSL, and a plurality of lower memory cell transistors MCT2 that aredisposed between the ground selection transistors GST and the switchingelements SW. The ground selection transistor GST and the lower memorycell transistors MCT2 may be connected in series to each other.

A string selection line SSL and upper word lines WL1(0) to WL1(3), whichare disposed between the bit lines BL and the switching elements SW, maybe used as gate electrodes of the string selection transistor SST andupper memory cell transistors MCT1, respectively. A ground selectionline GSL and lower word lines WL2(0) to WL2(3), which are disposedbetween the common source line CSL and the switching elements SW, may beused as gate electrodes of the ground selection transistor GST and lowermemory cell transistors MCT2, respectively. Each of the upper and lowermemory cell transistors MCT1 and MCT2 may include a data storageelement.

A plurality of the upper strings CSTR1 respectively connected to the bitlines BL may be connected in common to the one lower string CSTR2 thatis connected to the common source line CSL. Thus, the upper stringsCSTR1 including the string selection transistors SST respectivelyconnected to the bit lines BL may share the ground selection transistorGST included in the one lower string CSTR2. In other words, the upperstrings CSTR1 that are connected to different bit lines so as to beoperated independently of each other may be connected in common to theone lower string CSTR2 to share the ground selection transistor GST, soa highly integrated semiconductor memory device may be realized.

FIG. 18 is a cross-sectional view illustrating a semiconductor memorydevice according to still another embodiment of the inventive concepts.In the present embodiment, the same elements as described in the aboveembodiments will be indicated by the same reference numerals or the samereference designators, and thus descriptions of these elements will onlybe mentioned briefly or may be omitted altogether.

Referring to FIG. 18, the memory structure 20 may include asemiconductor layer 130, stack structures ST on the semiconductor layer130, and a plurality of active pillars AP penetrating the stackstructures ST. The stack structures ST may include insulating patterns155 and electrodes between the insulating patterns 155.

The electrodes of each of the stack structures ST may be sequentiallystacked on the semiconductor layer 130 in a vertical direction (e.g., athird direction D3). The electrodes may include a string selection lineSSL, word lines, and a ground selection lines GSL. The string selectionline SSL may be between the word lines and the bit lines BL. The groundselection line GSL may be between the word lines and a common sourceline CSL. The word lines of each of the stack structures ST may besequentially stacked on the semiconductor layer 130. The stringselection line SSL and the ground selection line GSL may be on the wordlines. The string selection line SSL and the ground selection line GSLmay be spaced apart from each other in the second direction D2 by atrench 165. The word lines may include upper word lines WL1 that arebetween the semiconductor layer 130 and the string selection line SSLand lower word lines WL2 that are between the semiconductor layer 130and the ground selection line GSL. The upper word lines WL1 may bespaced apart from the lower word lines WL2 in the second direction D2 bythe trench 165.

A device isolation pattern 177 may be provided between the stringselection line SSL and the ground selection line GSL and between theupper word lines WL1 and the lower word lines WL2. The device isolationpattern 177 may have a linear shape and may extend in the firstdirection D1. The device isolation pattern 177 may fill the trench 165and may include at least one of a silicon oxide layer, a silicon nitridelayer, or a silicon oxynitride layer.

The active pillars AP may be arranged along the first direction D1 whenviewed from a plan view. Each of the active pillars AP may includevertical portions VP that penetrate the stack structures ST and ahorizontal portion HP that is disposed under the stack structures ST toconnect the vertical portions VP of two adjacent active pillars AP toeach other. The vertical portions VP may be provided in vertical holespenetrating the stack structures ST. The horizontal portions HP may beprovided in horizontal recesses in an upper portion of the semiconductorlayer 130. One of the vertical portions VP of each active pillar AP maybe connected to the common source line CSL and the other of the verticalportions VP of each active pillar AP may be connected to one of the bitlines BL. The horizontal portion HP may be provided between thesemiconductor layer 130 and the stack structures ST to connect thevertical portions VP to each other.

In more detail, the vertical portions VP of each active pillar AP mayinclude a first vertical portion VP1 that penetrates the stringselection line SSL and the upper word lines WL1, and a second verticalportion VP2 that penetrates the ground selection line GSL and the lowerword lines WL2. The first vertical portion VP1 may be connected to oneof the bit lines BL through a pad PAD and a bit line contact 185, andthe second vertical portion VP2 may be connected to the common sourceline CSL. The horizontal portion HP may extend from under the upper wordlines WL1 to under the lower word lines WL2 so as to electricallyconnect the first vertical portion VP1 to the second vertical portionVP2.

Each of the active pillars AP may include a semiconductor pattern thatpenetrates the stack structure ST so as to be electrically coupled tothe semiconductor layer 130. The semiconductor pattern included in thevertical portion VP may cover inner sidewalls of the vertical holes. Thesemiconductor pattern included in the horizontal portion HP may cover aninner surface of the horizontal recess. Other elements of thesemiconductor memory device according to the present embodiment may bethe same as or similar to corresponding elements of the semiconductormemory device described above with reference to FIGS. 5A and 5B.

In the semiconductor memory devices according to embodiments of theinventive concepts, the logic structure driving the memory structure maybe disposed under the memory structure, so that the integration densityof the semiconductor memory device may be improved. In addition,according to embodiments of the inventive concepts, the page buffer maybe divided into first and second page buffers that are disposed atopposed sides of the memory structure, thereby increasing the widths ofthe connection conductive lines that electrically connect the bit linesto the page buffer. As a result, the resistance characteristics of theconnection conductive lines may be improved, so the electricalcharacteristics of the semiconductor memory device may be improved.

Furthermore, since the widths of the connection conductive lines areincreased, it is possible to easily arrange and form the connectioncontacts electrically connecting the bit lines to the connectionconductive lines. As a result, the highly integrated semiconductormemory device may be more easily realized.

While the inventive concepts have been described above with reference toexample embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirits and scopes of the inventive concepts. Therefore, itshould be understood that the above embodiments are not limiting, butillustrative. Thus, the scope of the inventive concepts are to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing description.

1. A semiconductor memory device, comprising: a substrate having anupper surface that extends in a first direction and in a seconddirection that is perpendicular to the first direction; a logic circuiton the upper surface of the substrate, the logic circuit comprising afirst page buffer and a second page buffer; a memory cell array on thelogic circuit opposite the substrate, the memory cell array comprising:a semiconductor layer; a pair of stack structures spaced apart from eachother in the second direction, respective ones of the pair of stackstructures comprising a plurality of electrodes that are stacked on thesemiconductor layer; a first bit line and a second bit line on the pairof stack structures, the first and second bit lines extending in thesecond direction and being adjacent to each other in the firstdirection; and an isolation insulating layer extending in the firstdirection, the isolation insulating layer between the pair of stackstructures; an upper insulating layer on the pair of stack structures; afirst connection contact penetrating the upper insulating layer and thesemiconductor layer to electrically connect the first bit line to thefirst page buffer; and a second connection contact penetrating theisolation insulating layer and the semiconductor layer to electricallyconnect the second bit line to the second page buffer.
 2. Thesemiconductor memory device of claim 1, wherein the second page bufferis spaced apart from the first page buffer in the second direction. 3.The semiconductor memory device of claim 1, wherein the substratecomprises a first connection region, a second connection region, and acircuit region therebetween, wherein the memory cell array is on thecircuit region, and wherein the first connection contact is on the firstconnection region, and the second connection contact is on the circuitregion.
 4. The semiconductor memory device of claim 3, wherein a maximumwidth of a first portion of the first bit line that is on the firstconnection region exceeds a maximum width of a second portion of thefirst bit line that crosses the memory cell array.
 5. The semiconductormemory device of claim 1, further comprising: a first connectionconductive line extending in the second direction, the first connectionconductive line disposed between the first connection contact and thefirst page buffer to electrically connect the first connection contactto the first page buffer; and a second connection conductive lineextending in the second direction, the second connection conductive linedisposed between the second connection contact and the second pagebuffer to electrically connect the second connection contact to thesecond page buffer.
 6. The semiconductor memory device of claim 5,wherein an average width in the first direction of the first connectionconductive line is greater than an average width in the first directionof the first bit line.
 7. The semiconductor memory device of claim 5,wherein an average width in the first direction of the second connectionconductive line is greater than an average width in the first directionof the second bit line.
 8. A semiconductor memory device, comprising: asubstrate comprising an upper surface that extends in a first directionand in a second direction that is perpendicular to the first direction;a logic circuit comprising a first page buffer on the upper surface ofthe substrate; a memory cell array on the logic circuit opposite thesubstrate; a plurality of bit lines on the memory cell array, the bitlines extending in the second direction to at least partly cross thememory cell array, the bit lines comprising first bit lines and secondbit lines that are alternately and repeatedly arranged in the firstdirection; a plurality of first connection conductive pads between thelogic circuit and the memory cell array; and a plurality of firstconnection contacts between respective ones of the first connectionconductive pads and respective ones of the first bit lines, wherein thefirst bit lines are electrically connected to the first page bufferthrough respective ones of the first connection contacts and respectiveones of the first connection conductive pads, wherein a first pitchbetween the first connection conductive pads is greater than a secondpitch between the bit lines, and wherein an average width in the firstdirection of one of the first connection conductive pads is greater thanan average width in the first direction of one of the first bit lines towhich the one of the first connection conductive pads is electricallyconnected.
 9. The semiconductor memory device of claim 8, wherein thelogic circuit further comprises a second page buffer that is spacedapart from the first page buffer in the second direction, and whereinthe second bit lines are electrically connected to the second pagebuffer.
 10. The semiconductor memory device of claim 9, furthercomprising: a plurality of second connection conductive pads between thelogic circuit and the memory cell array; and a plurality of secondconnection contacts between respective ones of the second connectionconductive pads and respective ones of the second bit lines, wherein thesecond bit lines are electrically connected to the second page bufferthrough respective ones of the second connection contacts and respectiveones of the second connection conductive pads, wherein a third pitchbetween the second connection conductive pads is greater than the secondpitch between the bit lines, and wherein an average width in the firstdirection of one of the second connection conductive pads is greaterthan an average width in the first direction of one of the second bitlines to which the one of the second connection conductive pads iselectrically connected.
 11. The semiconductor memory device of claim 8,wherein a third pitch between the first connection contacts issubstantially the same as the first pitch.
 12. The semiconductor memorydevice of claim 8, further comprising a plurality of first connectionconductive lines extending in the second direction, the first connectionconductive lines disposed between respective ones of the firstconnection conductive pads and the first page buffer to electricallyconnect respective ones of the first connection conductive pads to thefirst page buffer, wherein the average width of the one of the firstconnection conductive pads is greater than an average width in the firstdirection of one of the first connection conductive lines to which theone of the first connection conductive pads is electrically connected.13. The semiconductor memory device of claim 12, wherein a third pitchbetween the first connection conductive lines is substantially the sameas the first pitch.
 14. The semiconductor memory device of claim 12,wherein the average width of the one of the first connection conductivelines is greater than the average width of the one of the first bitlines.
 15. The semiconductor memory device of claim 8, wherein thesubstrate comprises a first connection region, a second connectionregion, and a circuit region therebetween, wherein the memory cell arrayis on the circuit region, and wherein the first connection conductivepads and the first connection contacts are on the first connectionregion.
 16. A semiconductor memory device, comprising: a substratecomprising an upper surface that extends in a first direction and in asecond direction that is perpendicular to the first direction; a logiccircuit comprising a first page buffer on the upper surface of thesubstrate; a memory cell array on the logic circuit opposite thesubstrate; a plurality of bit lines on the memory cell array, the bitlines extending in the second direction to at least partly cross thememory cell array; a first connection conductive line on the logiccircuit and extending in the second direction, the first connectionconductive line electrically connected to the first page buffer; a firstconnection conductive pad on the first connection conductive line andelectrically connected to the first connection conductive line; and afirst connection contact vertically extending to electrically connect afirst of the bit lines to the first connection conductive pad, whereinan average width in the first direction of the first connectionconductive line is greater than an average width in the first directionof the first of the bit lines, and wherein an average width in the firstdirection of the first connection conductive pad is greater than theaverage width of the first connection conductive line.
 17. Thesemiconductor memory device of claim 16, wherein the logic circuitfurther comprises a second page buffer that is spaced apart from thefirst page buffer in the second direction, and wherein a second of thebit lines is electrically connected to the second page buffer.
 18. Thesemiconductor memory device of claim 17, further comprising: a secondconnection conductive line on the logic circuit and extending in thesecond direction, the second connection conductive line electricallyconnected to the second page buffer; a second connection conductive padon the second connection conductive line and electrically connected tothe second connection conductive line; and a second connection contactvertically extending to electrically connect the second of the bit linesto the second connection conductive pad, wherein an average width in thefirst direction of the second connection conductive line is greater thanan average width in the first direction of the second of the bit lines,and wherein an average width in the first direction of the secondconnection conductive pad is greater than the average width of thesecond connection conductive line.
 19. The semiconductor memory deviceof claim 18, wherein the substrate comprises a first connection region,a second connection region, and a circuit region therebetween, whereinthe memory cell array is on the circuit region, wherein the firstconnection conductive pad and the first connection contact are on thefirst connection region, and wherein the second connection conductivepad and the second connection contact are on the second connectionregion.
 20. The semiconductor memory device of claim 16, wherein thefirst connection conductive pad comprises a plurality of firstconnection conductive pads that are electrically connected to respectiveones of the bit lines, and wherein a first pitch between the firstconnection conductive pads is greater than a second pitch between thebit lines.